DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 113

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

5.4
5.4.1
There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to
WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0
share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6 , and IRQ2 to IRQ0 can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0 to use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an
independent vector address.
Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
Interrupt control levels can be specified by the ICR settings.
The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
Interrupt Sources
External Interrupts
Note: n = 7 to 0
IRQn input
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
IRQnSCA, IRQnSCB
detection circuit
Edge/level
Clear signal
S
R
IRQnF
Rev. 2.00 Mar 21, 2006 page 73 of 518
Q
IRQnE
Section 5 Interrupt Controller
IRQn interrupt
request
REJ09B0299-0200