DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 176

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 8 14-Bit PWM Timer (PWMX)
8.3.3
DACR selects test mode, enables the PWM outputs, and selects the output phase and operating
speed.
Bit
7
6
5, 4 —
3
2
1
0
Rev. 2.00 Mar 21, 2006 page 136 of 518
REJ09B0299-0200
Bit
Name
TEST
PWME
OEB
OEA
OS
CKS
PWM (D/A) Control Register (DACR)
Initial
Value
0
All 1
0
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Test Mode
Selects test mode, which is used in testing this LSI. Normally
this bit should be cleared to 0.
0: PWM (D/A) in user state: Normal operation
1: PWM (D/A) in test state: Correct conversion results
unobtainable
PWM Enable
Starts or stops the PWM D/A counter (DACNT).
0: DACNT operates as a 14-bit up-counter
1: DACNT halts at H'0003
Reserved
These bits are always read as 1 and cannot be modified.
Output Enable B
Enables or disables output on PWM (D/A) channel B.
0: PWM (D/A) channel B output (at the PWX1 pin) is disabled
1: PWM (D/A) channel B output (at the PWX1 pin) is enabled
Output Enable A
Enables or disables output on PWM (D/A) channel A.
0: PWM (D/A) channel A output (at the PWX0 pin) is disabled
1: PWM (D/A) channel A output (at the PWX0 pin) is enabled
Output Select
Selects the phase of the PWM (D/A) output.
0: Direct PWM (D/A) output
1: Inverted PWM (D/A) output
Clock Select
Selects the PWM (D/A) resolution. If the system clock ( )
frequency is 10 MHz, resolutions of 100 ns and 200 ns, can be
selected.
0: Operates at resolution (T) = system clock cycle time (t
1: Operates at resolution (T) = system clock cycle time (t
cyc
cyc
)
)
2