DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 417

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
7
6
5
STR3 (TWRE = 1 or SELSTR3 = 0)
Bit Name Initial Value Slave Host Description
IBF3B
OBF3B
MWMF
0
0
0
R/(W) * R
R
R
R/W
R
R
Bidirectional Data Register Input Buffer Full
Set to 1 when the host processor writes to TWR15.
This is an internal interrupt source to the slave
processor (this LSI). IBF3B is cleared to 0 when the
slave processor reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
Bidirectional Data Register Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
TWR15. OBF3B is cleared to 0 when the host
processor reads TWR15.
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: [Setting condition]
When the slave processor writes to TWR15
Master Write Mode Flag
Set to 1 when the host processor writes to TWR0.
MWMF is cleared to 0 when the slave processor (this
LSI) reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 377 of 518
REJ09B0299-0200

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