DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 371

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

7. Notes on ICDR read at end of master reception
Clearing of the MST bit after completion of master transmission/reception, or other modifications
of IIC control bits to change the transmit/receive operating mode or settings, must be carried out
during interval (a) in figure 13.29 (after confirming that the BBSY bit in ICCR has been cleared to
0).
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
Internal clock
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR (ICDRR), and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been
released, then read ICDR with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
BBSY bit
SCL
SDA
ICXR.
Master receive mode
Bit 0
8
Figure 13.29 Notes on Reading Master Receive Data
(write 0 to BBSY and SCP)
for issuing stop condition
Execution of instruction
A
9
disabled period
ICDR read
Confirmation of stop
condition issuance
(read BBSY = 0)
Rev. 2.00 Mar 21, 2006 page 331 of 518
Stop condition
Section 13 I
(a)
2
C Bus Interface (IIC)
REJ09B0299-0200
Start condition
issuance
Start condition