DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 367

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

13.5
The IIC has interrupt source IICI. Table 13.7 shows the interrupt sources and priority. Individual
interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the
interrupt controller independently.
Table 13.7 IIC Interrupt Sources
13.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal
Channel
0
1
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
conditions when accessing to ICDR.
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
Interrupt Sources
Usage Notes
Name
IICI0
IICI1
Enable Bit
IEIC
IEIC
Interrupt Source
I
request
I
request
2
2
C bus interface interrupt
C bus interface interrupt
Rev. 2.00 Mar 21, 2006 page 327 of 518
Section 13 I
Interrupt Flag
IRIC
IRIC
2
C Bus Interface (IIC)
REJ09B0299-0200
2
2
C bus output
C bus, neither
Priority
Low
High