DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 431

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15.4.2
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and
bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B 0000 in the slave’s synchronization return cycle, but with the chip’s LPC a
value of B 0000 is always returned.
If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the
host interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort) before state #12, registers and flags are not changed.
State
Count
1
2
3
4
5
6
7
8
9
10
11
12
13
Contents
Start
Cycle type/direction Host
Address 1
Address 2
Address 3
Address 4
Turnaround
(recovery)
Turnaround
Synchronization
Data 1
Data 2
Turnaround
(recovery)
Turnaround
LPC I/O Cycles
I/O Read Cycle
Drive
Source
Host
Host
Host
Host
Host
Host
None
Slave
Slave
Slave
Slave
None
Value
(3 to 0)
0000
0000
Bits 15 to
12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
1111
ZZZZ
0000
Bits 3 to 0
Bits 7 to 4
1111
ZZZZ
Section 15 Host Interface LPC Interface (LPC)
Contents
Start
Cycle type/direction Host
Address 1
Address 2
Address 3
Address 4
Data 1
Data 2
Turnaround
(recovery)
Turnaround
Synchronization
Turnaround
(recovery)
Turnaround
Rev. 2.00 Mar 21, 2006 page 391 of 518
I/O Write Cycle
Drive
Source
Host
Host
Host
Host
Host
Host
Host
Host
None
Slave
Slave
None
REJ09B0299-0200
Value
(3 to 0)
0000
0010
Bits 15 to
12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
Bits 3 to 0
Bits 7 to 4
1111
ZZZZ
0000
1111
ZZZZ