DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 309

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

The I
optional function.
This LSI has a two-channel I
subset of the Philips I
controls the I
13.1
IFIIC60B_000020020800
Although the product type name is identical, please contact Renesas before using this optional
function on an F-ZTAT version product.
Selection of addressing format or non-addressing format
Conforms to Philips I
Two ways of setting slave address (I
Start and stop conditions generated automatically in master mode (I
Selection of the acknowledge output level in reception (I
Automatic loading of an acknowledge bit in transmission (I
Wait function in master mode (I
Wait function (I
Interrupt sources
2
C bus interface is provided as an optional function. Note the following point when using this
I
Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait can be cleared by clearing the interrupt flag.
A wait request can be generated by driving the SCL pin low after data transfer.
The wait request is cleared when the next transfer becomes possible.
Data transfer end (including when a transition to transmit mode with I
when ICDR data is transferred, or during a wait state)
Address match: When any slave address matches or the general call address is received in
slave receive mode with I
arbitration)
Start condition detection (in master mode)
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
Features
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
Section 13 I
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface. The I
2
C bus format (including address reception after loss of master
2
C bus format)
2
C bus format)
2
2
C Bus Interface (IIC)
C bus format)
2
C bus interface conforms to and provides a
Rev. 2.00 Mar 21, 2006 page 269 of 518
2
C bus format)
2
C bus format)
Section 13 I
2
C bus format)
2
2
C bus format occurs,
C Bus Interface (IIC)
REJ09B0299-0200