DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 491

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Power-Down Modes
19.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS
bit in TCSR (WDT_1) is cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU’s internal registers, on-chip RAM data, I/O ports, and the
states of on-chip peripheral modules other than the SCI and PWMX, are retained as long as the
prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7),
the RES pin input, or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt
with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software
standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2,
IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side.
When the RES pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation
stabilizes, the CPU begins reset exception handling.
When the STBY pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 19.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 2.00 Mar 21, 2006 page 451 of 518
REJ09B0299-0200

Related parts for DF2110BVTE10