DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 350

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
12. The IRIC flag is set to 1 in either of the following cases.
13. Read the IRTR flag in ICSR.
14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
15. Clear the WAIT bit in ICMR to cancel the wait mode.
16. Read the last ICDR receive data.
17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
Rev. 2.00 Mar 21, 2006 page 310 of 518
REJ09B0299-0200
User processing
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
Execute step [12] to read the IRIC flag to detect the end of reception.
Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the
WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop
condition is executed, the stop condition may not be issued correctly.)
is high, and generates the stop condition.
(master output)
(master output)
(slave output)
At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next data.
SDA
SCL
SDA
Master tansmit mode
ICDR
IRTR
IRIC
2
C Bus Interface (IIC)
Figure 13.15 Example of Master Receive Mode Operation Timing
[1] TRS cleared to 0
9
A
IRIC cleard to 0
Master receive mode
[2] ICDR read
Bit 7
(dummy read)
1
(MLS = ACKB = 0, WAIT = 1)
Bit 6
2
Bit 5
3
Data 1
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1 Bit 0
7
[6] IRIC clear
(to end wait insertion)
8
[4]IRTR=0
[3]
A
[4] IRTR=1
9
[3]
[5] ICDR read
Bit 7
Data 1
(Data 1)
1
Bit 6
2
Data 2
[6] IRIC clear
Bit 5
3
Bit 4
4
Bit 3
5