DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 87

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Prior to executing BCLR:
BCLR instruction executed:
After executing BCLR:
Operation:
1. When the BCLR instruction is executed, first the CPU reads P4DDR.
2. The CPU clears bit 0 of the read data to 0, changing data to H'FE.
3. The CPU writes H'FE to DDR, completing execution of BCLR.
As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin.
However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.
Input/output
Pin state
DDR
DR
BCLR #0,
Input/output
Pin state
DDR
DR
Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a
value of H'3F, but the value read by the CPU is H'FF.
@P4DDR
P47
Input
Low
level
0
1
P47
Output
Low
level
1
1
P46
Input
High
level
0
0
P46
Output
High
level
1
0
The BCLR instruction is executed for DDR in port 4.
P45
Output
Low
level
1
0
P45
Output
Low
level
1
0
P44
Output
Low
level
1
0
P44
Output
Low
level
1
0
P43
Output
Low
level
1
0
P43
Output
Low
level
1
0
Rev. 2.00 Mar 21, 2006 page 47 of 518
P42
Output
Low
level
1
0
P42
Output
Low
level
1
0
P41
Output
Low
level
1
0
P41
Output
Low
level
1
0
REJ09B0299-0200
Section 2 CPU
P40
Output
Low
level
1
0
P40
Input
High
level
0
0