DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 476

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 Clock Pulse Generator
Table 18.3 External Clock Input Conditions
Item
External clock input pulse
width low level
External clock input pulse
width high level
External clock rising time
External clock falling time
Clock pulse width low level
Clock pulse width high level
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (t
signal should be set to low to hold it in reset state. Table 18.4 shows the external clock output
stabilization delay time. Figure 18.6 shows the timing of the external clock output stabilization
delay time.
Rev. 2.00 Mar 21, 2006 page 436 of 518
REJ09B0299-0200
DEXT
) has passed. As the clock signal output is not determined during the t
EXTAL
t
EXr
Figure 18.5 External Clock Input Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
t
EXH
Min
40
40
0.4
80
0.4
80
V
CC
= 2.7 to 3.6 V
Max
10
10
0.6
0.6
t
EXf
t
EXL
Unit
ns
ns
ns
ns
t
ns
t
ns
cyc
cyc
V
CC
Test Conditions
Figure 18.5
× 0.5
< 5 MHz
5 MHz
5 MHz
5 MHz
DEXT
cycle, a reset
Figure
21.5

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