DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 534

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 21 Electrical Characteristics
21.1.3
Figure 21.3 shows the test conditions for the AC characteristics.
Clock Timing: Table 21.5 shows the clock timing. The clock timing specified here covers clock
( ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation
settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section
18, Clock Pulse Generator.
Table 21.5 Clock Timing
Conditions: V
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Oscillation settling time at reset (crystal)
Oscillation settling time in software
standby (crystal)
External clock output stabilization delay
time
Rev. 2.00 Mar 21, 2006 page 494 of 518
REJ09B0299-0200
Chip output
pin
AC Characteristics
CC
= 2 MHz to maximum operating frequency, T
= 3.0 V to 3.6 V, V
C
Figure 21.3 Output Load Circuit
CC
R
B = 3.0 V to 5.5 V, V
H
Symbol
t
t
t
t
t
t
t
t
cyc
CH
CL
Cr
Cf
OSC1
OSC2
DEXT
V
CC
R
L
Min
100
30
30
—
—
20
8
500
SS
a
Condition
= 0 V,
= –20 to +75°C
10 MHz
C = 30 pF: All output ports
R
R
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V
L
H
Max
500
—
—
20
20
—
—
—
= 2.4 k
= 12 k
Unit
ns
ns
ns
ns
ns
ms
ms
µs
Reference
Figure 21.5
Figure 21.6
Figure 21.7