DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 409

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
2
Bit Name Initial Value Slave Host Description
ABRT
IBFIE3
IBFIE2
0
0
0
R/W
R/(W) * —
R/W
R/W
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRIE = 0 in LADR3]
IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed
1: Input data register (IDR2) receive completed
IDR3 and TWR Receive Completion Interrupt
completed interrupt requests disabled
interrupt requests disabled
interrupt requests enabled
Writing 0 after reading ABRT = 1
LPC hardware reset and LPC software reset
LPC hardware shutdown and LPC software
shutdown
Input data register (IDR3) receive completed
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
completed interrupt requests enabled
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 369 of 518
REJ09B0299-0200

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