DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 490

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 19 Power-Down Modes
Figure 19.2 shows an example of medium-speed mode timing.
19.4
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the peripheral modules do not stop. The contents of the CPU’s internal
registers are retained.
Sleep mode is exited by any interrupt, the RES pin, or the STBY pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode
is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU.
Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation
stabilization time has passed, driving the RES pin high causes the CPU to start reset exception
handling.
When the STBY pin level is driven low, sleep mode is cancelled and a transition is made to
hardware standby mode.
Rev. 2.00 Mar 21, 2006 page 450 of 518
REJ09B0299-0200
peripheral module clock
Bus master clock
Internal address bus
Internal write signal
φ
,
Sleep Mode
Figure 19.2 Medium-Speed Mode Timing
SBYCR
Medium-speed mode
SBYCR