DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 238

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 10 8-Bit Timer (TMR)
10.7
If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSX and CKSY bits in TCRXY.
10.7.1
When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the
timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X
occupying the lower 8 bits.
Note: The program development tool (emulator) does not support 16-bit count mode.
10.7.2
When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1,
TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.
Note:
Rev. 2.00 Mar 21, 2006 page 198 of 518
REJ09B0299-0200
Setting of compare-match flags
Counter clear specification
Pin output
The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs.
The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs.
If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare-
match, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y
are also cleared when counter clear by the TMRIY pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of
TCNT_X can be cleared by the counter.
Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance
with the upper 8-bit compare-match conditions.
Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance
with the lower 8-bit compare-match conditions.
The program development tool (emulator) does not support compare-match count mode.
16-Bit Count Mode
Compare-Match Count Mode
TMR_Y and TMR_X Cascaded Connection