DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 469

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

17.9
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
17.9.1
Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled
or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode,
software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control
registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2)
are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held
low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the
RES pin low for the RES pulse width specified in the AC Characteristics section.
17.9.2
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E
bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When
EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
17.9.3
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
When the flash memory of is read during programming/erasing (including vector read and
instruction fetch)
Immediately after exception handling (excluding a reset) during programming/erasing
When a SLEEP instruction is executed (transits to software standby mode, sleep mode, sub-
active mode, sub-sleep mode, or watch mode) during programming/erasing
Program/Erase Protection
Hardware Protection
Software Protection
Error Protection
Rev. 2.00 Mar 21, 2006 page 429 of 518
REJ09B0299-0200
Section 17 ROM