DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 160

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 I/O Ports
7.10.2
P9DR stores output data for the port 9 pins.
Bit
7
6
5
4
3
2
1
0
Note: * The initial value of bit 6 is determined according to the P96 pin state.
7.10.3
ICE
P97DDR
Pin Function
Note: * When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an
P96DDR
EXCLE
Pin Function
Note: * When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
Rev. 2.00 Mar 21, 2006 page 120 of 518
REJ09B0299-0200
P97/SDA0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0 and the P97DDR bit.
P96/ /EXCL
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P96DDR bit.
NMOS open-drain output, and has direct bus drive capability.
Bit Name
P97DR
P96DR
P95DR
P94DR
P93DR
P92DR
P91DR
P90DR
Port 9 Data Register (P9DR)
Pin Functions
Initial Value
0
Undefined *
0
0
0
0
0
0
P97 input pin
P96 input pin
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
With the exception of P96, if a port 9 read is
performed while P9DDR bits are set to 1, the
P9DR values are read directly, regardless of the
actual pin states. If a port 9 read is performed
while P9DDR bits are cleared to 0, the pin states
are read.
For P96, the pin state is always read.
0
0
EXCL input pin
P97 output pin
1
1
SDA0 I/O pin
output pin
1
1
0

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