DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 230

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 10 8-Bit Timer (TMR)
10.3.9
TCONRI controls the input capture function.
Bit
7 to 5
4
3 to 0
10.3.10 Timer Connection Register S (TCONRS)
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit
7
6 to 0
Rev. 2.00 Mar 21, 2006 page 190 of 518
REJ09B0299-0200
Bit Name
—
ICST
—
Bit Name
TMR_X/Y
—
Timer Connection Register I (TCONRI)
Initial Value
0
All 0
Initial Value
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The initial value should not be changed.
Input Capture Start Bit
TMR_X has input capture registers (TICRR and
TICRF). TICRR and TICRF can measure the width
of a pulse by means of a single capture operation
under the control of the ICST bit. When a rising edge
followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at
those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Reserved
The initial values should not be modified.
Description
TMR_X/TMR_Y Access Select
For details, see table 10.3.
0: The TMR_X registers are accessed at addresses
H'(FF)FFF0 to H'(FF)FFF5
1: The TMR_Y registers are accessed at addresses
H'(FF)FFF0 to H'(FF)FFF5
Reserved
The initial values should not be modified.