DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 125

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

To use the address break function, set each register as follows:
1. Set a break address in the A23 to A1 bits in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable the address break.
When the BIE bit is cleared to 0, an address break is not requested.
When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an
interrupt. The interrupt source should be determined by the interrupt handling routine if necessary.
5.7.4
1. In an address break, the break address should be an address where the first byte of the
2. In normal mode, addresses A23 to A16 are not compared.
3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and
4. An address break interrupt is generated by combining the internal prefetch signal and an
Figure 5.9 shows an example of address timing.
instruction exists. Otherwise, a break condition will not be satisfied.
RTE instruction are placed immediately prior to the address specified by BAR, a prefetch
signal to the address may be output to request an address break by executing these instruction.
It is necessary to take countermeasures: do not set a break address to an address immediately
after these instructions, or determine whether interrupt handling is performed by satisfaction of
a normal condition.
address. Therefore, the timing to enter the interrupt exception handling differs according to the
instructions at the specified and at prior addresses and execution cycles.
Usage Notes
Rev. 2.00 Mar 21, 2006 page 85 of 518
Section 5 Interrupt Controller
REJ09B0299-0200