DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 376

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 11 in
14. Notes on Arbitration Lost in master mode
Rev. 2.00 Mar 21, 2006 page 336 of 518
REJ09B0299-0200
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 13.35. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
The I
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I
figure 13.36.)
In multi-master mode, a bus conflict could happen. When The I
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
SDA
TRS
SCL
ICXR.
2
C bus interface recognizes the data in transmit/receive frame as an address when
transmission
2
C Bus Interface (IIC)
Data
The rise of the 9th clock is detected
8
2
C bus interface erroneously recognizes that the address call has occurred. (See
9
TRS bit setting
(a)
Figure 13.35 TRS Bit Set Timing in Slave Mode
ICDR dummy read
Restart condition
TRS bit setting is suspended in this period
1
Address reception
2
(b)
3
4
5
6
7
The rise of the 9th clock is detected
2
C bus interface is operated in
8
9
A