DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 335

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Bit Bit Name
4
ICDRE
Initial Value R/W
0
R
Description
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to ICDR
(ICDRT) or ICDR is initialized.
1: Indicates that data has been transferred from ICDRT to
ICDRS and is being transmitted, or the start condition has
been detected or transmission has been complete, thus
allowing the next data to be written to.
[Setting conditions]
[Clearing conditions]
Note that if the ACKE bit is set to 1 with I
enabling acknowledge bit decision, ICDRE is not set when
data transmission is completed while the acknowledge bit
is 1.
When ICDRE is set due to the condition (2) above, ICDRE
is temporarily cleared to 0 when data is written to ICDR
(ICDRT); however, since data is transferred from ICDRT to
ICDRS immediately, ICDRE is set to 1 again. Do not write
data to ICDR when TRS = 0 because the ICDRE flag value
is invalid during the time.
When the start condition is detected from the bus line
state with I
When data is transferred from ICDRT to ICDRS.
(1) When data transmission completed while ICDRE =
(2) When data is written to ICDR in transmit mode after
When data is written to ICDR (ICDRT).
When the stop condition is detected with I
or serial format.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3 to
CLR0 bits in DDCSWR.
0 (at the rise of the 9th clock pulse).
data transmission was completed while ICDRE = 1.
2
C bus format or serial format.
Rev. 2.00 Mar 21, 2006 page 295 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200
2
C bus format thus
2
C bus format