DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 321

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Bit Bit Name
5
4
3
MST
TRS
ACKE
Initial Value R/W
0
0
0
R/W
R/W
Description
[MST clearing conditions]
1. When 0 is written by software
2. When lost in bus contention in I
[MST setting conditions]
1. When 1 is written by software (for MST clearing
2. When 1 is written in MST after reading MST = 0 (for
[TRS clearing conditions]
1. When 0 is written by software (except for TRS setting
2. When 0 is written in TRS after reading TRS = 1 (for
3. When lost in bus contention in I
[TRS setting conditions]
1. When 1 is written by software (except for TRS clearing
2. When 1 is written in TRS after reading TRS = 0 (for
3. When 1 is received as the R/W bit after the first frame
Acknowledge Bit Decision and Selection
0: The value of the acknowledge bit is ignored, and
1: If the received acknowledge bit is 1, continuous transfer
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing of
the received data, for instance, or may be fixed at 1 and
have no significance.
mode
condition 1)
MST clearing condition 2)
condition 3)
TRS setting condition 3)
mode
condition 3)
TRS clearing condition 3)
address matching in I
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
is halted.
Rev. 2.00 Mar 21, 2006 page 281 of 518
Section 13 I
2
C bus format slave mode
2
2
C bus format master
C bus format master
2
C Bus Interface (IIC)
REJ09B0299-0200