DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 402

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Host Interface LPC Interface (LPC)
Bit
4
3
Rev. 2.00 Mar 21, 2006 page 362 of 518
REJ09B0299-0200
Bit Name Initial Value Slave Host Description
FGA20E
SDWNE
0
0
R/W
R/W
R/W
Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate
can be implemented by firmware operation of the
P81 output.
When the fast A20 gate function is enabled, the DDR
bit for P81 must not be set to 1.
0: Fast A20 gate function disabled
1: Fast A20 gate function enabled
LPC Software Shutdown Enable
Controls host interface shutdown. For details of the
LPC shutdown function, and the scope of initialization
by an LPC reset and an LPC shutdown, see section
15.4.4, Host Interface Shutdown Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
1: LPC hardware shutdown state setting enabled
[Setting condition]
Writing 1 after reading SDWNE = 0
Other function of pin P81 is enabled
GA20 output internal state is initialized to 1
GA20 pin output is open-drain (external VCC pull-
up resistor required)
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown release (rising edge of
LPCPD signal)
Hardware shutdown state when LPCPD signal is
low

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