DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 25

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
13.1 Features ............................................................................................................................. 269
13.2 Input/Output Pins .............................................................................................................. 272
13.3 Register Descriptions ........................................................................................................ 273
13.4 Operation .......................................................................................................................... 297
13.5 Interrupt Sources............................................................................................................... 327
13.6 Usage Notes ...................................................................................................................... 327
Section 14 Keyboard Buffer Controller
14.1 Features ............................................................................................................................. 339
14.2 Input/Output Pins .............................................................................................................. 340
14.3 Register Descriptions ........................................................................................................ 341
14.4 Operation .......................................................................................................................... 345
13.3.1 I
13.3.2 Slave Address Register (SAR) ............................................................................. 274
13.3.3 Second Slave Address Register (SARX) ............................................................. 275
13.3.4 I
13.3.5 I
13.3.6 I
13.3.7 DDC Switch Register (DDCSWR) ...................................................................... 292
13.3.8 I
13.4.1 I
13.4.2 Initialization ......................................................................................................... 299
13.4.3 Master Transmit Operation .................................................................................. 299
13.4.4 Master Receive Operation.................................................................................... 304
13.4.5 Slave Receive Operation...................................................................................... 311
13.4.6 Slave Transmit Operation .................................................................................... 319
13.4.7 IRIC Setting Timing and SCL Control ................................................................ 322
13.4.8 Noise Canceler ..................................................................................................... 325
13.4.9 Initialization of Internal State .............................................................................. 325
13.6.1 Module Stop Mode Setting .................................................................................. 338
14.3.1 Keyboard Control Register H (KBCRH) ............................................................. 341
14.3.2 Keyboard Control Register L (KBCRL) .............................................................. 343
14.3.3 Keyboard Data Buffer Register (KBBR) ............................................................. 344
14.4.1 Receive Operation................................................................................................ 345
14.4.2 Transmit Operation .............................................................................................. 346
14.4.3 Receive Abort ...................................................................................................... 349
14.4.4 KCLKI and KDI Read Timing............................................................................. 351
14.4.5 KCLKO and KDO Write Timing......................................................................... 352
2
2
2
2
2
2
2
C Bus Data Register (ICDR) ............................................................................. 273
C Bus Mode Register (ICMR) ........................................................................... 277
C Bus Control Register (ICCR) ......................................................................... 280
C Bus Status Register (ICSR)............................................................................ 288
C Bus Extended Control Register (ICXR)......................................................... 293
C Bus Data Format ............................................................................................ 297
C Bus Interface (IIC)
.................................................................................. 269
........................................................................ 339
Rev. 2.00 Mar 21, 2006 page xxiii of xxxviii