DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 31

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 10 8-Bit Timer (TMR)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10
Figure 10.11
Figure 10.12
Figure 10.13
Figure 10.14
Figure 10.15
Section 11 Watchdog Timer (WDT)
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Section 12 Serial Communication Interface (SCI)
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Block Diagram of WDT....................................................................................... 208
Watchdog Timer Mode (RST/NMI = 1) Operation ............................................. 215
Interval Timer Mode Operation ........................................................................... 216
OVF Flag Set Timing........................................................................................... 216
Output Timing of RESO signal............................................................................ 217
Writing to TCNT and TCSR (WDT_0) ............................................................... 218
Conflict between TCNT Write and Increment..................................................... 219
Sample Circuit for Resetting System by RESO Signal........................................ 220
Block Diagram of SCI ......................................................................................... 222
Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits).......................................................................................... 237
Receive Data Sampling Timing in Asynchronous Mode..................................... 239
Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) ......................................................................................... 240
Sample SCI Initialization Flowchart.................................................................... 241
Example of SCI Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 242
Sample Serial Transmission Flowchart................................................................ 243
Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ....................................... 175
Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ..................................... 176
Pulse Output Example ........................................................................................ 192
Count Timing for Internal Clock Input............................................................... 193
Count Timing for External Clock Input (Both Edges)........................................ 193
Timing of CMF Setting at Compare-Match........................................................ 194
Timing of Toggled Timer Output by Compare-Match A Signal ........................ 194
Timing of Counter Clear by Compare-Match..................................................... 195
Timing of Counter Clear by External Reset Input .............................................. 195
Timing of OVF Flag Setting............................................................................... 196
Timing of Input Capture Operation .................................................................... 199
Timing of Input Capture Signal (Input Capture Signal Is Input
during TICRR and TICRF Read)........................................................................ 200
Conflict between TCNT Write and Clear ........................................................... 202
Conflict between TCNT Write and Count-Up.................................................... 202
Conflict between TCOR Write and Compare-Match.......................................... 203
Rev. 2.00 Mar 21, 2006 page xxix of xxxviii