DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 12

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Rev. 2.00 Mar 21, 2006 page x of xxxviii
Item
9.3.6 Timer Interrupt
Enable Register (TIER)
9.3.7 Timer
Control/Status Register
(TCSR)
10.3.5 Timer
Control/Status Register
(TCSR)
10.3.10 Timer
Connection Register S
(TCONRS)
Table 10.3 Registers
Accessible by
TMR_X/TMR_Y
10.7.3 Input Capture
Operation
Figure 10.11 Timing of
Input Capture
Operation
13.3.5 I
Control Register
(ICCR)
Table 13.5 Flags and
Transfer States Slave
Mode)
13.4.4 Master
Receive Operation
Figure 13.11 Example
of Operation Timing
master Receive Mode
(MLS = WAIT = 0,
HNDS = 1)
2
C Bus
Page
153
154
188
190
191
199
280
283, 284
286
306
Revisions (See Manual for Details)
Initial value in bit 0 amended
(Before) 0
ICFB description in bit 6 amended
... When BUFEB =1, ICRB indicates that the old ICRB value ...
TCSR_Y
Initial value in bit 4 amended
(Before) 0
Bit name in bits 6 to 0 amended
(Before) (Blanc)
Table 10.3 amended
TCNT_X
Figure 10.11 amended
TCNT_X
MST and TRS description in bits 5 and 4 amended
.... In slave receive mode with I
first frame immediately after the start condition ...
R/W in bit 1 amended
R/(W)*
Table 13.5 amended
Figure 13.11 amended
[2] ICDR read (Dummy read)
MST
0
0
0
0
TRS
1
1
1
1
BBSY ESTP STOP IRTR
1
1
1
1
0
0
0
0
(After) 1
(After) 1
0
0
0
0
(After)
—
—
—
1 /0 *
2
AASX AL
—
—
—
—
0
—
0
0
2
AAS
0
—
0
0
C bus format, the R/W bit in the
ADZ
0
0
0
0
ACKB ICDRF ICDRE State
0
0
0
0
—
—
—
—
0
1
0
1
ICDR write with the
above state
Transmission
with ICDRE = 1
ICDR write with the
above state
Automatic data
transfer from ICDRT
to ICDRS with the
above state
nd
e