DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 21

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

7.12 Port B ................................................................................................................................ 127
Section 8 14-Bit PWM Timer (PWMX)
8.1
8.2
8.3
8.4
8.5
8.6
Section 9 16-Bit Free-Running Timer (FRT)
9.1
9.2
9.3
9.4
9.5
7.11.3 Port A Input Data Register (PAPIN).................................................................... 123
7.11.4 Pin Functions ....................................................................................................... 124
7.11.5 Port A Input Pull-Up MOS .................................................................................. 126
7.12.1 Port B Data Direction Register (PBDDR)............................................................ 127
7.12.2 Port B Output Data Register (PBODR) ............................................................... 127
7.12.3 Port B Input Data Register (PBPIN) .................................................................... 128
7.12.4 Pin Functions ....................................................................................................... 128
7.12.5 Port B Input Pull-Up MOS .................................................................................. 129
Features ............................................................................................................................. 131
Input/Output Pins .............................................................................................................. 132
Register Descriptions ........................................................................................................ 132
8.3.1
8.3.2
8.3.3
Bus Master Interface ......................................................................................................... 137
Operation .......................................................................................................................... 138
Usage Note........................................................................................................................ 146
8.6.1
Features ............................................................................................................................. 147
Input/Output Pins .............................................................................................................. 149
Register Descriptions ........................................................................................................ 149
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
Operation .......................................................................................................................... 159
9.4.1
Operation Timing.............................................................................................................. 159
9.5.1
9.5.2
PWM (D/A) Counters H and L (DACNTH, DACNTL)...................................... 133
PWM (D/A) Data Registers A and B (DADRA, DADRB) ................................. 134
PWM (D/A) Control Register (DACR) ............................................................... 136
Module Stop Mode Setting .................................................................................. 146
Free-Running Counter (FRC) .............................................................................. 150
Output Compare Registers A and B (OCRA, OCRB) ......................................... 150
Input Capture Registers A to D (ICRA to ICRD) ................................................ 150
Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 151
Output Compare Register DM (OCRDM) ........................................................... 151
Timer Interrupt Enable Register (TIER) .............................................................. 152
Timer Control/Status Register (TCSR) ................................................................ 153
Timer Control Register (TCR) ............................................................................. 156
Timer Output Compare Control Register (TOCR) .............................................. 157
Pulse Output......................................................................................................... 159
FRC Increment Timing ........................................................................................ 159
Output Compare Output Timing .......................................................................... 160
....................................................................... 131
.............................................................. 147
Rev. 2.00 Mar 21, 2006 page xix of xxxviii