DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 334

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 I
Bit Bit Name
5
Rev. 2.00 Mar 21, 2006 page 294 of 518
REJ09B0299-0200
ICDRF
2
C Bus Interface (IIC)
Initial Value R/W
0
R
Description
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) status in receive mode.
0: Indicates that the data has been already read from
ICDR (ICDRR) or ICDR is initialized.
1: Indicates that data has been received successfully and
transferred from ICDRS to ICDRR, and the data is ready to
be read out.
[Setting conditions]
[Clearing conditions]
When ICDRF is set due to the condition (2) above, ICDRF
is temporarily cleared to 0 when ICDR (ICDRR) is read;
however, since data is transferred from ICDRS to ICDRR
immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Be sure to read data from ICDR in
receive mode (TRS = 0).
When data is received successfully and transferred
from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF = 0
(2) When ICDR is read successfully in receive mode
When ICDR (ICDRR) is read.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3 to
CLR0 bits in DDCSWR.
(at the rise of the 9th clock pulse).
after data was received while ICDRF = 1.

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