DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 171

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It
can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
8.1
Figure 8.1 shows a block diagram of the PWM (D/A) module.
DTCH80BA_010020020900
Division of pulse into multiple base cycles to reduce ripple
Two resolution settings
The resolution can be set equal to one or two system clock cycles.
Two base cycle settings
The base cycle can be set equal to T
Four operating speeds
Four operation clocks (by combination of two resolution settings and two base cycle settings)
PWX0
PWX1
Legend:
DACR
DADRA
DADRB
DACNT
Features
: PWM D/A control register
: PWM D/A data register A
: PWM D/A data register B
: PWM D/A counter
Section 8 14-Bit PWM Timer (PWMX)
Select clock
Control
logic
Figure 8.1 PWM (D/A) Block Diagram
Internal clock
Base cycle compare match A
Fine–adjustment pulse addition
Base cycle compare match B
Fine–adjustment pulse addition
φ
φ/2
Base cycle overflow
Clock
64 or T
A
B
Comparator A
Comparator B
256, where T is the resolution.
DACNT
DACR
Rev. 2.00 Mar 21, 2006 page 131 of 518
Section 8 14-Bit PWM Timer (PWMX)
DADRA
DADRB
Internal data bus
Module data bus
Bus interface
REJ09B0299-0200