DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 213

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

TIMH265A_000020020800
This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on
the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a
variety of applications, such as generation of counter reset, interrupt requests, and pulse output
with an arbitrary duty cycle using a compare-match signal with two registers.
This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels.
10.1
Selection of clock sources
Selection of three ways to clear the counters
Timer output controlled by two compare-match signals
Cascading of two channels
TMR_0, TMR_1: The counter input clock can be selected from six internal clocks and an
external clock
TMR_Y, TMR_X: The counter input clock can be selected from six internal clocks *
an external clock
The counters can be cleared on compare-match A or compare-match B, or by an external
reset signal.
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle.
Cascading of TMR_0 and TMR_1
Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1
as the lower half (16-bit count mode).
TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count
mode).
Cascading of TMR_Y and TMR_X *
Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X
as the lower half (16-bit count mode).
TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count
mode).
Features
Section 10 8-Bit Timer (TMR)
2
Rev. 2.00 Mar 21, 2006 page 173 of 518
Section 10 8-Bit Timer (TMR)
REJ09B0299-0200
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