DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 330

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 I
Bit Bit Name
2
1
Rev. 2.00 Mar 21, 2006 page 290 of 518
REJ09B0299-0200
AAS
ADZ
2
C Bus Interface (IIC)
Initial Value R/W
0
0
R/(W) * Slave Address Recognition Flag
R/(W) * General Call Address Recognition Flag
Description
In I
the first frame following a start condition matches bits SVA6
to SVA0 in SAR, or if the general call address (H'00) is
detected.
[Setting condition]
When the slave address or general call address (one frame
including a R/W bit is H'00) is detected in slave receive
mode and FS = 0 in SAR
[Clearing conditions]
In I
the first frame following a start condition is the general call
address (H'00).
[Setting condition]
When the general call address (one frame including a R/W
bit is H'00) is detected in slave receive mode and FS = 0 or
FSX = 0
[Clearing conditions]
If a general call address is detected while FS = 1 and FSX
= 0, the ADZ flag is set to 1; however, the general call
address is not recognized (AAS flag is not set to 1).
2
2
When ICDR is written to (transmit mode) or read from
(receive mode)
When 0 is written in AAS after reading AAS = 1
In master mode
When ICDR is written to (transmit mode) or read from
(receive mode)
When 0 is written in ADZ after reading ADZ = 1
In master mode
C bus format slave receive mode, this flag is set to 1 if
C bus format slave receive mode, this flag is set to 1 if

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