DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 397

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
IFHSTL0A_010020020800
This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33-MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC
module supports only I/O read cycle and I/O write cycle transfers.
It is also provided with power-down functions that can control the PCI clock and shut down the
host interface.
15.1
Supports LPC interface I/O read cycles and I/O write cycles
Has three register sets comprising data and status registers
Supports SERIRQ
Eleven interrupt sources
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively. A fast
A20 gate function is also provided.
The I/O address can be set for channel 3. Sixteen bidirectional data register bytes can be
manipulated in addition to the basic register set.
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
Features
Section 15 Host Interface LPC Interface (LPC)
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 357 of 518
REJ09B0299-0200

Related parts for DF2110BVTE10