DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 326

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Table 13.5 Flags and Transfer States (Slave Mode)
MST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Legend:
0:
1:
—:
Rev. 2.00 Mar 21, 2006 page 286 of 518
REJ09B0299-0200
TRS
0
0
1 /0 *
0
1 /0 *
1
1
1
1
1
1
0
0
0
0
0
—
0-state retained
1-state retained
Previous state retained
1
1
BBSY ESTP STOP IRTR
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
C Bus Interface (IIC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 /0 *
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1 *
3
0
0
0
0
1
—
1 /0 *
—
—
—
1 /0 *
1 /0 *
—
—
—
1 /0 *
—
1
2
2
2
AASX AL
0
0
0
0
1
—
—
—
—
—
—
—
—
—
—
—
—
0
0
—
—
—
—
—
0
—
0
0
—
0
—
0
0
—
AAS
0
0
1
1
0
—
—
0
—
0
0
—
0
—
0
0
—
ADZ
0
0
0
1
0
0
0
0
0
0
0
—
0
—
0
0
—
ACKB ICDRF ICDRE State
0
0
0
0
0
1
0
0
0
0
0
—
—
—
—
—
—
—
—
1
1
1
—
—
—
—
—
—
1
0
1
0
1
—
0
1
1
1
1
—
1
0
1
0
1
—
—
—
—
—
0
Idle state (flag
clearing required)
Start condition
detected
SAR match in first
frame (SARX
General call address
match in first frame
(SARX
SARS match in first
frame (SAR
Transmission end
(ACKE = 1 and
ACKB = 1)
Transmission end
with ICDRE = 0
ICDR write with the
above state
Transmission end
with ICDRE = 1
ICDR write with the
above state
Automatic data
transfer from ICDRT
to ICDRS with the
above state
Reception end with
ICDRF = 0
ICDR read with the
above state
Reception end with
ICDRF = 1
ICDR read with the
above state
Automatic data
transfer from ICDRS
to ICDRR with the
above state
Stop condition
detected
H'00)
SARX)
SAR)