DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 94

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 MCU Operating Modes
Bit
3
2
1
0
3.3
3.3.1
The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM
is enabled.
3.3.2
The CPU can access a 64-kbyte address space in normal single-chip mode. The on-chip ROM is
enabled. The CPU can access a 56-kbyte address space in mode 3.
Rev. 2.00 Mar 21, 2006 page 54 of 518
REJ09B0299-0200
Bit Name
FLSHE
ICKS1
ICKS0
Operating Mode Descriptions
Mode 2
Mode 3
Initial Value
0
0
0
0
R/W
R/W
R/(W)
R/W
R/W
Description
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on-
chip peripheral modules (PCSR, SYSCR2).
0: Registers in power-down state and control
registers of on-chip peripheral modules are accessed
in an area from H'(FF)FF80 to H'(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H'(FF)FF80 to H'(FF)FF87.
Reserved
The initial value should not be changed.
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, refer to section 10.3.4, Timer
Control Register (TCR).

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