DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 18

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

2.8
2.9
Section 3 MCU Operating Modes
3.1
3.2
3.3
3.4
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
Rev. 2.00 Mar 21, 2006 page xvi of xxxviii
2.7.8
2.7.9
Processing States............................................................................................................... 44
Usage Notes ...................................................................................................................... 46
2.9.1
2.9.2
2.9.3
2.9.4
MCU Operating Mode Selection ...................................................................................... 49
Register Descriptions ........................................................................................................ 49
3.2.1
3.2.2
3.2.3
Operating Mode Descriptions ........................................................................................... 54
3.3.1
3.3.2
Address Map in Each Operating Mode ............................................................................. 55
Exception Handling Types and Priority ............................................................................ 57
Exception Sources and Exception Vector Table ............................................................... 58
Reset.................................................................................................................................. 59
4.3.1
4.3.2
4.3.3
Interrupt Exception Handling............................................................................................ 60
Trap Instruction Exception Handling................................................................................ 60
Stack Status after Exception Handling.............................................................................. 61
Usage Note........................................................................................................................ 62
Features ............................................................................................................................. 63
Input/Output Pins .............................................................................................................. 65
Register Descriptions ........................................................................................................ 65
5.3.1
5.3.2
5.3.3
5.3.4
Memory Indirect—@@aa:8 ................................................................................ 41
Effective Address Calculation ............................................................................. 42
Note on TAS Instruction Usage ........................................................................... 46
Note on STM/LDM Instruction Usage ................................................................ 46
Bit Manipulation Instructions .............................................................................. 46
EEPMOV Instruction........................................................................................... 48
Mode Control Register (MDCR) ......................................................................... 50
System Control Register (SYSCR) ...................................................................... 51
Serial Timer Control Register (STCR) ................................................................ 53
Mode 2 ................................................................................................................. 54
Mode 3 ................................................................................................................. 54
Reset Exception Handling.................................................................................... 59
Interrupts after Reset............................................................................................ 60
On-Chip Peripheral Modules after Reset Is Cancelled ........................................ 60
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 66
Address Break Control Register (ABRKCR)....................................................... 67
Break Address Registers A to C (BARA to BARC) ............................................ 67
IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 68
.......................................................................................... 63
......................................................................................... 57
.................................................................................. 49