DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 414

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 15 Host Interface LPC Interface (LPC)
15.3.7
The STR registers are 8-bit registers that indicate status information during host interface
processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits for both
the host processor and the slave processor (this LSI). However, only 0 can be written to bit 0 of
STR1 to STR3 and bits 6 and 4 of STR3, from the slave processor (this LSI), in order to clear the
flags to 0. The registers selected from the host processor according to the I/O address are shown in
the following table. For information on STR3 selection, see section 15.3.3, LPC Channel 3
Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is
transferred to the host processor. The initial values of STR1 to STR3 are H'00.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
Rev. 2.00 Mar 21, 2006 page 374 of 518
REJ09B0299-0200
Status Registers 1 to 3 (STR1 to STR3)
I/O Address
Bit 3
0
0
Bit 2
1
1
Bit 1
0
1
Bit 0
0
0
Transfer Cycle Host Register Selection
I/O read
I/O read
STR1 read
STR2 read