DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 362

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 I
13.4.7
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
Rev. 2.00 Mar 21, 2006 page 322 of 518
REJ09B0299-0200
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
IRIC Setting Timing and SCL Control
2
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
C Bus Interface (IIC)
7
7
7
7
Figure 13.25 IRIC Setting Timing and SCL Control (1)
8
8
8
8
2
C bus format, no wait)
9
A
9
A
Clear IRIC
Clear IRIC
1
1
Write to ICDR (transmit)
or read from ICDR (receive)
2
2
3
1
1
3
Clear IRIC

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