DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 210

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 9 16-Bit Free-Running Timer (FRT)
9.7.4
When the internal clock is changed, the changeover may cause FRC to increment. This depends on
the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock ( ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 9.3, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also cause FRC to increment.
Rev. 2.00 Mar 21, 2006 page 170 of 518
REJ09B0299-0200
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match
Switching of Internal Clock and FRC Operation
Compare-match signal
Internal write signal
OCRAR (OCRAF)
(When Automatic Addition Function Is Used)
Address
OCRA
FRC
φ
Write cycle of OCRAR/OCRAF
Automatic addition is not performed
because compare-match signals are disabled.
OCRAR (OCRAF)
T 1
address
Disabled
Old data
T 2
N
N
New data
N+1