DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 433

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15.4.3
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1
of data following an H'D1 command and outputs it at the gate A20 pin.
Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E =
0. When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. The
state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2.
The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host
processor can manipulate the output from this pin by sending commands and data. This function
is only available via the IDR1 register. The host interface decodes commands input from the host.
When an H'D1 host command is detected, bit 1 of the data following the host command is output
from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster
than the regular processing using interrupts. Table 15.3 shows the conditions that set and clear
GA20 (P81). Figure 15.4 shows the GA20 output in flowchart form. Table 15.4 indicates the
GA20 output signal values.
Table 15.3 GA20 (P81) Set/Clear Timing
Pin Name
GA20 (P81)
A20 Gate
Setting Condition
When bit 1 of the data that follows an
H'D1 host command is 1
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 393 of 518
Clearing Condition
When bit 1 of the data that follows an
H'D1 host command is 0
REJ09B0299-0200