DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 314

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
If I
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set I
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
13.3.2
SAR sets the slave address and selects the communication format. If the LSI is in slave mode with
the I
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Bit Bit Name
7
6
5
4
3
2
1
0
Rev. 2.00 Mar 21, 2006 page 274 of 518
REJ09B0299-0200
2
C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
2
C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Slave Address Register (SAR)
2
C Bus Interface (IIC)
Initial Value R/W
0
0
0
0
0
0
0
0
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
C to receive mode before reading from ICDR.
Description
Slave Address 6 to 0
Set a slave address.
Format Select
Selects the communication format together with the FSX bit
in SARX. Refer to table 13.2.
This bit should be set to 0 when general call address
recognition is performed.