DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 22

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

9.6
9.7
Section 10 8-Bit Timer (TMR)
10.1 Features ............................................................................................................................. 173
10.2 Input/Output Pins .............................................................................................................. 177
10.3 Register Descriptions ........................................................................................................ 177
10.4 Operation .......................................................................................................................... 192
10.5 Operation Timing.............................................................................................................. 193
Rev. 2.00 Mar 21, 2006 page xx of xxxviii
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
9.5.10 Mask Signal Generation Timing .......................................................................... 165
Interrupt Sources............................................................................................................... 166
Usage Notes ...................................................................................................................... 167
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
10.3.1 Timer Counter (TCNT)........................................................................................ 179
10.3.2 Time Constant Register A (TCORA)................................................................... 179
10.3.3 Time Constant Register B (TCORB) ................................................................... 179
10.3.4 Timer Control Register (TCR) ............................................................................. 180
10.3.5 Timer Control/Status Register (TCSR) ................................................................ 184
10.3.6 Time Constant Register (TCORC)....................................................................... 189
10.3.7 Input Capture Registers R and F (TICRR and TICRF)........................................ 189
10.3.8 Timer Input Select Register (TISR) ..................................................................... 189
10.3.9 Timer Connection Register I (TCONRI) ............................................................. 190
10.3.10 Timer Connection Register S (TCONRS)............................................................ 190
10.3.11 Timer XY Control Register (TCRXY) ................................................................ 191
10.4.1 Pulse Output......................................................................................................... 192
10.5.1 TCNT Count Timing............................................................................................ 193
10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 194
10.5.3 Timing of Timer Output at Compare-Match........................................................ 194
10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 195
10.5.5 TCNT External Reset Timing .............................................................................. 195
10.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 196
FRC Clear Timing................................................................................................ 161
Input Capture Input Timing ................................................................................. 161
Buffered Input Capture Input Timing .................................................................. 162
Timing of Input Capture Flag (ICF) Setting ........................................................ 163
Timing of Output Compare Flag (OCF) setting................................................... 164
Timing of FRC Overflow Flag Setting ................................................................ 164
Automatic Addition Timing................................................................................. 165
Conflict between FRC Write and Clear ............................................................... 167
Conflict between FRC Write and Increment........................................................ 168
Conflict between OCR Write and Compare-Match ............................................. 169
Switching of Internal Clock and FRC Operation ................................................. 170
Module Stop Mode Setting .................................................................................. 172
........................................................................................ 173