DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 313

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

13.3
The I
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer
to section 3.2.3, Serial Timer Control Register (STCR).
13.3.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is internally divided into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among
these three registers are performed automatically in accordance with changes in the bus state, and
they affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag is
0) after successful transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRT to ICDRS.
If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data
is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If I
(TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
I
I
I
I
Slave address register (SAR)
Second slave address register (SARX)
I
DDC switch register (DDCSWR)
2
2
2
2
2
C bus control register (ICCR)
C bus status register (ICSR)
C bus data register (ICDR)
C bus mode register (ICMR)
C bus extended control register (ICXR)
2
C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
Register Descriptions
I
2
C Bus Data Register (ICDR)
2
C bus format, writing transmit data to ICDR should be
Rev. 2.00 Mar 21, 2006 page 273 of 518
Section 13 I
2
C is in receive mode
2
C Bus Interface (IIC)
REJ09B0299-0200