DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 338

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Table 13.6 I
Legend
S
SLA
R/W
A
DATA
P
Rev. 2.00 Mar 21, 2006 page 298 of 518
REJ09B0299-0200
SDA
SCL
S
Start condition. The master device drives SDA from high to low while SCL is high
Slave address. The master device selects the slave device.
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high
2
C Bus Interface (IIC)
2
C Bus Data Format Symbols
SLA
1–7
R/W
8
A
9
Figure 13.5 I
1–7
DATA
2
C Bus Timing
8
A
9
1–7
DATA
8
A/A
9
P