DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 460

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 17 ROM
17.7.1
Table 17.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data,
3. When the boot program is initiated, this LSI measures the low-level period of asynchronous
4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of
5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses
6. Before branching to the programming control program (H'FFE088 in the RAM area), this LSI
Rev. 2.00 Mar 21, 2006 page 420 of 518
REJ09B0299-0200
the host beforehand. Prepare a programming control program in accordance with the
description in section 17.8, Flash Memory Programming/Erasing. In boot mode, if any data
exists in the flash memory (except in the case that all data are 1), all blocks in the flash
memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery
when user program mode cannot be executed because the program to be initiated in user
program mode was mistakenly erased.
1 stop bit, and no parity.
SCI communication data (H'00) transmitted continuously from the host. This LSI then
calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match
that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins
should be pulled up on the board if necessary. After the reset ends, it takes approximately 100
states before this LSI is ready to measure the low-level period.
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to this LSI. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and this LSI. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 17.6.
H'FFE080 to H'FFE87F*
from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to H'FFE087.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program. Figure 17.6 shows the on-chip RAM area in boot mode.
terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but
the adjusted bit rate value remains set in BRR. Therefore, the programming control program
can still use it for transfer of write data or verify data with the host. The TxD1 pin is in high-
level output state. The contents of the CPU general registers are undefined immediately after
branching to the programming control program. These registers must be initialized at the
beginning of the programming control program, since the stack pointer (SP), in particular, is
used implicitly in subroutine calls, etc.
Boot Mode
1
is the area to which the programming control program is transferred