DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 86

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 2 CPU
2.9
2.9.1
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++
compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers
ER0, ER1, ER4 and ER5.
2.9.2
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by
one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers: ER0–ER1, ER2–ER3, or ER4–ER5
Three registers: ER0–ER2 or ER4–ER6
Four registers: ER0–ER3
The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and
H8/300 series C/C++ compilers.
2.9.3
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where a register containing a
write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a
bit other than the bit to be manipulated.
Example: The BCLR instruction is executed for DDR in port 4.
P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at
P46. P45 to P40 are output pins and output low-level signals. The following shows an example in
which P40 is set to be an input pin with the BCLR instruction.
Rev. 2.00 Mar 21, 2006 page 46 of 518
REJ09B0299-0200
Usage Notes
Note on TAS Instruction Usage
Note on STM/LDM Instruction Usage
Bit Manipulation Instructions