DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 346

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 13 I
Receive Operation Using the Wait Function:
Figures 13.13 and 13.14 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Rev. 2.00 Mar 21, 2006 page 306 of 518
REJ09B0299-0200
(master output)
(master output)
(slave output)
User processing
ICDRR
ICDRF
SCL
SDA
SDA
IRTR
IRIC
(master output)
(master output)
(slave output)
User processing
Master transmit mode
ICDRR
ICDRF
SCL
SDA
SDA
IRTR
IRIC
Figure 13.11 Example of Operation Timing in Master Receive Mode
Figure 13.12 Example of Stop Condition Issuance Operation Timing
2
C Bus Interface (IIC)
Bit 1
Data 1
Data 2
7
[4] IRIC clear
Bit 0
A
9
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
8
[1] TRS = 0 clear
[6] Set ACKB = 1
A
[3]
9
SCL is fixed low until ICDR is read
SCL is fixed low until ICDR is read
Master receive mode
[1] IRIC clear
Bit 7
1
[7] ICDR read
(MLS = WAIT = 0, HNDS = 1)
(Data 2)
Bit 7
Bit 6
1
2
Bit 6
Bit 5
2
3
Data 1
[2] ICDR read
Undefined value
(Dummy read)
Bit 5
Bit 4
3
Data 2
Data 3
4
Bit 4
Bit 3
4
5
Bit 3
Bit 2
5
6
Bit 2
Bit 1
6
7
[4] IRIC clear
Bit 1
Bit 0
SCL is fixed low until
stop condition is issued
[9] IRIC clear
7
8
Bit 0
[3]
A
8
9
SCL is fixed low until ICDR is read
[11] Set BBSY = 0 and
(Stop condition instruction issuance)
A
[8]
9
SCP = 0
[5] ICDR read
(Data 1)
Data 1
Stop condition generation
Bit 7
[10] ICDR read
1
Data 2
(Data 3)
Bit 6
2
Data 3