DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 377

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

15. Note on ICDR read in transmit mode and ICDR write in receive mode
16. Note on ACKE and TRS bits in slave mode
I
(Master transmit mode)
Other device
(Master transmit mode)
I
(Slave receive mode)
2
2
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
(b) Set the MST bit to 1.
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0),
the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode
or write to ICDR after setting transmit mode.
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
C bus interface
C bus interface
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Figure 13.36 Diagram of Erroneous Operation when Arbitration is Lost
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
2
C protocol, the same problem may occur when the MST
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as
• When the receive data matches to
an address
the address set in the SAR or SARX
register, the I
as a slave device
receive mode
SLA
DATA1
DATA2
Rev. 2.00 Mar 21, 2006 page 337 of 518
Transmit data does not match
2
C bus interface operates
R/W
Section 13 I
A
A
2
C Bus Interface (IIC)
DATA4
DATA3
REJ09B0299-0200
Data contention
A
A