DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 10

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 2.00 Mar 21, 2006 page viii of xxxviii
Item
5.6.2 Interrupt Control
Mode 1
Figure 5.6 Flowchart
of Procedure Up to
6.1 Bus Control
Register (BCR)
7.1 Overview
7.4.4 Pin Functions
7.9.3 Pin Functions
8.1 Features
Figure 8.1 PWM (D/A)
Block Diagram
Page
81
89
91
100
116
131
Revisions (See Manual for Details)
Figure 5.6 amended
(Before) IFBFI3
Initial value in bit 2 amended
(Before) 0
Description amended
(Before) Ports 1 to 3 and 6 have an input pull-up MOS control
register (PCR), in addition to DDR and DR, to control ...
(After) Ports 1 to 3 and 6 have an input pull-up MOS control
register (PCR), in addition to DDR, to control ...
Note * amended
Note: * The combination of bits not described ... m = 3 to 1:
LPC input/output pins (SERIRQ, LCLK, LRESET, LFRAME,
LAD3 to LAD0) ...
Table amended
IRQ5 input pin*
Figure 8.1 amended
PWX0
PWX1
P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME,
P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0
P86/IRQ5/SCK1/SCL1
Select clock
(After) 1
Control
logic
1
(After) IBFI3
Internal clock
Base cycle compare match A
Fine–adjustment pulse addition A
Base cycle compare match B
Fine–adjustment pulse addition B
φ
φ/2
Clock
Comparator A
Comparator B

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