DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 38

• Manufacturer Part Number: DF2110BVTE10
• Description: MCU 3V 64K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2110BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2110BVTE10; HD64F2110BVTE10

Section 12 Serial Communication Interface (SCI)
Table 12.1
Table 12.2
Table 12.3
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.9
Table 12.10 SCI Interrupt Sources ............................................................................................. 262
Section 13 I
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7
Table 13.8
Table 13.9
Table 13.10 I
Section 14 Keyboard Buffer Controller
Table 14.1
Section 15 Host Interface LPC Interface (LPC)
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10 Host Address Example ........................................................................................... 406
Rev. 2.00 Mar 21, 2006 page xxxvi of xxxviii
Pin Configuration ................................................................................................... 223
Relationships between N Setting in BRR and Bit Rate B ...................................... 232
BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 233
BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 234
Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 235
Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 235
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 236
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 236
Serial Transfer Formats (Asynchronous Mode) ..................................................... 238
SSR Status Flags and Receive Data Handling........................................................ 245
Pin Configuration ................................................................................................... 272
Communication Format.......................................................................................... 276
I
Flags and Transfer States (Master Mode) .............................................................. 285
Flags and Transfer States (Slave Mode)................................................................. 286
I
IIC Interrupt Sources.............................................................................................. 327
I
Permissible SCL Rise Time (t
Pin Configuration ................................................................................................... 340
Pin Configuration ................................................................................................... 359
Register Selection................................................................................................... 372
GA20 (P81) Set/Clear Timing................................................................................ 393
Scope of Host Interface Pin Shutdown................................................................... 397
Scope of Initialization in Each Host Interface Mode.............................................. 398
Frame Configuration of Serial Interrupt Transfer Cycle ........................................ 401
Receive Complete Interrupts and Error Interrupt ................................................... 403
HIRQ Setting and Clearing Conditions.................................................................. 404
2
Fast A20 Gate Output Signals ............................................................................... 395
C Bus Interface (IIC)
2
2
2
2
C Transfer Rate .................................................................................................... 279
C Bus Data Format Symbols................................................................................ 298
C Bus Timing (SCL and SDA Outputs)............................................................... 328
C Bus Timing (with Maximum Influence of t
sr
) Values ................................................................. 328
Sr
/t
Sf
)............................................... 330