DF2110BVTE10 Renesas Electronics America, DF2110BVTE10 Datasheet - Page 344

MCU 3V 64K 100-TQFP

DF2110BVTE10

Manufacturer Part Number
DF2110BVTE10
Description
MCU 3V 64K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2110BVTE10

Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
82
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2110BVTE10
HD64F2110BVTE10

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2110BVTE10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 I
13.4.4
In I
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 13.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
Rev. 2.00 Mar 21, 2006 page 304 of 518
REJ09B0299-0200
2
C bus format master receive mode, the master device outputs the receive clock, receives data,
Master Receive Operation
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode
2
C Bus Interface (IIC)
No
No
Read IRIC flag in ICCR
Set HNDS = 1 in ICXR
Set ACKB = 0 in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Set ACKB = 1 in ICSR
Clear IRIC flag in ICCR
Set TRS = 0 in ICCR
Master receive mode
Set TRS = 1 in ICCR
Set BBSY = 0 and
SCP = 0 in ICCR
Last receive?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
No
Yes
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
[4] Clear IRIC flag.
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
[8] Wait for 1 byte to be received.
[9] Clear IRIC flag.
[10] Read the receive data.
[11] Set stop condition issuance.
(HNDS = 1)
(Set IRIC at the rise of the 9th clock for the receive frame)
Dummy read to start receiving if the first frame is
the last receive data.
Generate stop condition.

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